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I'm trying to understand mipmapping.

It makes sense that you would have many pictures of your textures at different resolutions, and use the closest ones in size to what you need in order to avoid moiré patterns--that's logical. But a lot of the diagrams I've seen split out the R, G, and B channels: for example splitting a square into quarters, in which the top left is the red component of an image, the top right is green, the bottom left is blue, and the bottom right recursively splits the image up again, at a lower resolution.

So what's the point of splitting up the RGB? Why not just have a bunch of different-sized images of your texture? It seems that splitting them up is wasted work, since you'll ultimately just have to put them together again.

(There is an example of this phenomenon on the Wikipedia page for mipmapping, under the "Mechanism" heading.)

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Re separating RGB, I guess you are referring to Lance Williams' "Pyramidal Parametrics" paper.

I suspect he did it that way to fit in with the graphics system he had, but on modern GPUs (at least since I started developing them in 1992) the channels are not separate. The MIP map chain is likely to be just a set of $N \times M$, $\lfloor \frac{N}{2} \rfloor \times \lfloor \frac{M}{2}\rfloor, ..., 1\times1 $ images possibly arranged semi-contiguously in memory.

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    $\begingroup$ I just looked at the paper--yes, you're right. I also edited the question to include a reference to the Wikipedia page, that shows this phenomenon. Thanks. I think that this is my answer. $\endgroup$
    – Adam Smith
    Sep 27, 2022 at 0:38
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    $\begingroup$ Simon F is right! When trying to conserve space for 3 channels, the 2 x 2 split, r,g,b in 3 of the quarters, the next smaller mip level occupying the 4th quarter, is an elegant way pack everything when limiting mipmapping to square powers of 2. Modern GPUs support rectangular mimaps without power of 2 constraints, but with the constraint that all pixel formats are (likely) to be power of 2 bytes. Addressing constraints align pixels to avoid crossing cache lines; further constraints can cause small mips to waste alot of space, different per generation of HW. $\endgroup$
    – user2500
    Sep 27, 2022 at 17:31

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